1. Field of the Invention
The present invention relates generally to methods of forming MOS transistors, and more particularly to methods of simultaneously forming MOS transistors and a capacitor, an electrically erasable and programmable read only memory or a resistance on a substrate having gate insulation layers of varying thicknesses.
2. Discussion of Related Art
In a semiconductor integrated circuit (IC), electrical devices such as a transistor, a capacitor and a resistance are integrated into a chip. Therefore, methods for effectively integrating these electrical devices into a chip have been developed. For example, a method of simultaneously forming a plate electrode of a poly-insulation-poly (PIP) capacitor and a gate electrode of a MOS transistor is taught in U.S. Pat. No. 6,303,455, entitled “Method of fabricating capacitor”.
There have been extensive studies on simultaneously employing logic technologies for processing data (e.g., CPU technologies) and memory technologies for storing data. In addition, transistor technologies have been adapted to the logic and memory technologies. The current supplying ability of a transistor, and its low leakage current and high breakdown voltage characteristics are important in the memory technology. Therefore, a novel method to effectively embody MOS transistors having insulation layers of varying thicknesses in a single chip is needed.